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January 2024 term · Computer System Design · BSCS3031

Computer System Design Quiz 2: 24 March 2024 (January 2024 term)

The IIT Madras BS Computer System Design (Computer System Design) Quiz 2 paper sat on 24 Mar 2024, in the January 2024 term: 15 questions for 50 marks in 120 minutes. Every question is below with its answer. Take it as a timed mock test to be marked, or read it through first.

Questions
15
Marks
50
Duration
120 min
MCQ
9
Numerical
5
MSQ
1

Updated

Official paper: IIT M DEGREE AN EXAM QDB2 24 Mar 2024 · No negative marking.

Question 1

+1 markOne correct option

In a J-K flipflop, when J = 1 and K = 1, it toggles the flipflop’s state.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • A

    TRUE

Question 2

+1 markOne correct option

A multiplexer is a digital circuit that selects one of several input signals and forwards it to a single output line.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • A

    TRUE

Question 3

+1 markOne correct option

In a NAND-based gated D latch, when the write enable input is 1, it denotes the Memory Hold state.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 4

+1 markOne correct option

In a positive-edge-triggered D flipflop, if the D input is 1 and the clock signal transitions from low to high, Q output is 0.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 5

+1 markOne correct option

Sequential circuits utilize feedback loops, while combinational circuits do not.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • A

    TRUE

Question 6

+5 marksNumerical answer
Show answer

Correct answer: 2

Question 7

+5 marksNumerical answer

Consider the circuit diagram using j-K flipflop as shown below. Assuming it was initially cleared to 0, state the output Y for the next 4 clock pulses.

Show answer

Correct answer: 1010

Question 8

+4 marksOne correct option
  1. A
  2. B
  3. C
  4. D
Show answer

Correct answer

  • C

Question 9

+5 marksOne correct option
  1. A
  2. B
  3. C
  4. D
  5. E
Show answer

Correct answer

  • B

Question 10

+5 marksOne correct option
  1. A
  2. B
  3. C
  4. D
Show answer

Correct answer

  • D

Question 11

+5 marksOne or more correct options

Choose the correct options

Select all that apply.

  1. A
  2. B
  3. C
  4. D
Show answer

Correct answers

  • B
  • C

Question 12

+3 marksOne correct option

Based on below minterm, answer the given subquestions.

What will be the minimization expression?

  1. A
  2. B
  3. C
  4. D
Show answer

Correct answer

  • B

Question 13

+3 marksNumerical answer

Based on below minterm, answer the given subquestions.

If we want to design the given minterm using 2:1 multiplexers, what is the minimum number of multiplexers required?

Show answer

Correct answer: 2

Question 14

+4 marksNumerical answer

Consider a gated D-Latch constructed using NAND gates. The initial input (at 0 ns) is D = 1, and the write enable is high. The write enable toggles between high and low every 5 ns. The input D changes from 0 to 1 and from 1 to 0 every 6 seconds. What will be the output Q after 16 ns?

Show answer

Correct answer: 1

Question 15

+6 marksNumerical answer

Consider the circuit consisting of three D flipflops and one NAND gate as shown below.The initial states are Q1=1, Q2=0, and Q3=1. What is the output (Q1,Q2,Q3) after 4 clock pulses?

Show answer

Correct answer: 111