Question 1
In a J-K flipflop, when J = 1 and K = 1, it toggles the flipflop’s state.
TRUE
FALSE

The IIT Madras BS Computer System Design (Computer System Design) Quiz 2 paper sat on 24 Mar 2024, in the January 2024 term: 15 questions for 50 marks in 120 minutes. Every question is below with its answer. Take it as a timed mock test to be marked, or read it through first.
In a J-K flipflop, when J = 1 and K = 1, it toggles the flipflop’s state.
TRUE
FALSE
Correct answer
TRUE
A multiplexer is a digital circuit that selects one of several input signals and forwards it to a single output line.
TRUE
FALSE
Correct answer
TRUE
In a NAND-based gated D latch, when the write enable input is 1, it denotes the Memory Hold state.
TRUE
FALSE
Correct answer
FALSE
In a positive-edge-triggered D flipflop, if the D input is 1 and the clock signal transitions from low to high, Q output is 0.
TRUE
FALSE
Correct answer
FALSE
Sequential circuits utilize feedback loops, while combinational circuits do not.
TRUE
FALSE
Correct answer
TRUE
Correct answer: 2
Consider the circuit diagram using j-K flipflop as shown below. Assuming it was initially cleared to 0, state the output Y for the next 4 clock pulses.
Correct answer: 1010
Correct answer
Correct answer
Correct answer
Choose the correct options
Correct answers
Based on below minterm, answer the given subquestions.
What will be the minimization expression?
Correct answer
Based on below minterm, answer the given subquestions.
If we want to design the given minterm using 2:1 multiplexers, what is the minimum number of multiplexers required?
Correct answer: 2
Consider a gated D-Latch constructed using NAND gates. The initial input (at 0 ns) is D = 1, and the write enable is high. The write enable toggles between high and low every 5 ns. The input D changes from 0 to 1 and from 1 to 0 every 6 seconds. What will be the output Q after 16 ns?
Correct answer: 1
Consider the circuit consisting of three D flipflops and one NAND gate as shown below.The initial states are Q1=1, Q2=0, and Q3=1. What is the output (Q1,Q2,Q3) after 4 clock pulses?
Correct answer: 111