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September 2023 term · Computer System Design · BSCS3031

Computer System Design Quiz 2: 3 December 2023 (September 2023 term)

The IIT Madras BS Computer System Design (Computer System Design) Quiz 2 paper sat on 3 Dec 2023, in the September 2023 term: 15 questions for 50 marks in 120 minutes. Every question is below with its answer. Take it as a timed mock test to be marked, or read it through first.

Questions
15
Marks
50
Duration
120 min
MCQ
11
Numerical
2
MSQ
2
Take as mock testPractise with answers

Updated

Official paper: IIT M DEGREE AN2 EXAM QDB2 03 Dec 2023 · No negative marking.

Question 1

+1 markOne correct option

In a J-K flipflop, when J = 0 and K = 0, it toggles the flipflop’s state.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 1 on its own page

Question 2

+1 markOne correct option

In a positive-edge-triggered D flipflop, if the D input is 0 and the clock signal transitions from low to high, Q output is 1.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 2 on its own page

Question 3

+1 markOne correct option

In a NAND-based gated D latch, when the write enable input is 0, it denotes the Memory Hold state.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • A

    TRUE

Question 3 on its own pageAlso asked in Quiz 2 16 Aug 2026

Question 4

+1 markOne correct option

In a NAND-based gated D latch is edge-triggered, while a D flip-flop is level-sensitive.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 4 on its own page

Question 5

+1 markOne correct option

Master-slave J-K flipflops are capable of preventing race-around conditions, whereas regular JK flipflops lack this capability.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • A

    TRUE

Question 5 on its own page

Question 6

+4 marksOne correct option

The Boolean function for a combinational circuit with four inputs is represented by the following K-map.

AB \ CD00011110
001011
010110
110100
101001

Which literal will be present twice in the minimized SOP expression?

  1. A

    A

  2. B

    B

  3. C

    C

  4. D

    D

Show answer

Correct answer

  • D

    D

Question 6 on its own page

Question 7

+4 marksOne correct option

Consider the following expression:

Which of the following K-maps represents the expression correctly?

  1. A
  2. B
  3. C
  4. D
Show answer

Correct answer

  • D
Question 7 on its own page

Question 8

+4 marksNumerical answer

Consider a function, f which has four input variables (x, y, z, w). The function is defined to be high when the number is divided by 4 leaves the remainder of 1. Draw the Karnaugh Map (K-Map) for this function. Given inputs x, y, z, and w, along with their complements, if we want to implement the minimized expression using only 2-input NOR gates, what is the minimum number of NOR gates required?

Show answer

Correct answer: 1

Question 8 on its own page

Question 9

+4 marksOne or more correct options

Select all that apply.

  1. A

    The flipflop remains in reset state when inputs are changed to J = 1,K = 0

  2. B

    The flipflop remains in reset state even when inputs are changed to J = 1,K = 1

  3. C

    The outputs of the flipflop will toggle when inputs are changed to J = 1,K = 1

  4. D

    The flipflop will go into set state when inputs are changed to J = 1,K = 0

Show answer

Correct answers

  • A

    The flipflop remains in reset state when inputs are changed to J = 1,K = 0

  • B

    The flipflop remains in reset state even when inputs are changed to J = 1,K = 1

Question 9 on its own page

Question 10

+4 marksOne or more correct options

Select all that apply.

  1. A
  2. B
  3. C
  4. D
Show answer

Correct answers

  • A
  • D
Question 10 on its own page

Question 11

+5 marksNumerical answer

A half adder is implemented using XOR and AND gates, and a full adder is implemented using two half adders and an OR gate. The propagation delay of AND gate is half of that of the XOR gate and the propagation delay of OR gate is 1.6 nanoseconds. If a 4-bit ripple carry adder is implemented using four full adders, then what will be the total propagation time of this adder circuit, considering the delay of one XOR gate is 4 nanoseconds.

Show answer

Correct answer: 32

Question 11 on its own page

Question 12

+5 marksOne correct option

In the circuit shown below, D1 and D2 are positive triggered D flipflops, x1 and x2 are input of D1 and D2 flipflop. Choose the correct timing diagram of the output Y.

  1. A
  2. B
  3. C
  4. D
Show answer

Correct answer

  • B
Question 12 on its own page

Question 13

+5 marksOne correct option

We want to implement a 2-bit Gray code counter( an output sequence changing from 00 → 01 → 11 → 10 → 00) using the J-K flipflops as shown in the figure below. What should be the values of J1, K1, J2 and K2?

  1. A
  2. B
  3. C
  4. D
Show answer

Correct answer

  • C
Question 13 on its own page

Question 14

+5 marksOne correct option

Consider the circuit diagram as shown below. Assuming it was initially cleared to 0, state the output Y for the next 4 clock pulses.
Note: 1st one J-K flipflop 2nd one is D flipflop

  1. A

    0101

  2. B

    1010

  3. C

    1100

  4. D

    0011

Show answer

Correct answer

  • B

    1010

Question 14 on its own page

Question 15

+5 marksOne correct option

We want to implement circuit that output sequence changing from 000 → 001 → 011 → 111 → 000 using J-K flipflops, as shown in the figure below. What combination of gates should GT1 and GT2 be?

  1. A

    OR, AND

  2. B

    AND, XOR

  3. C

    OR, XOR

  4. D

    AND, AND

Show answer

Correct answer

  • D

    AND, AND

Question 15 on its own page