Question 3
In a NAND-based gated D latch, when the write enable input is 0, it denotes the Memory Hold state.
TRUE
FALSE
Question 3: In a NAND-based gated D latch, when the write enable inpu…
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Question 3 of 15 in the IIT Madras BS Computer System Design (Computer System Design) Quiz 2 paper sat on 3 Dec 2023, in the September 2023 term (IIT M DEGREE AN2 EXAM QDB2 03 Dec 2023). It carries 1 mark.
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