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Computer System Design · Quiz 2 · 3 Dec 2023 · September 2023 term

Question 11: A half adder is implemented using XOR and AND gates, and…

Question 11

+5 marksNumerical answer

A half adder is implemented using XOR and AND gates, and a full adder is implemented using two half adders and an OR gate. The propagation delay of AND gate is half of that of the XOR gate and the propagation delay of OR gate is 1.6 nanoseconds. If a 4-bit ripple carry adder is implemented using four full adders, then what will be the total propagation time of this adder circuit, considering the delay of one XOR gate is 4 nanoseconds.

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Correct answer: 32

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Question 11 of 15 in the IIT Madras BS Computer System Design (Computer System Design) Quiz 2 paper sat on 3 Dec 2023, in the September 2023 term (IIT M DEGREE AN2 EXAM QDB2 03 Dec 2023). It carries 5 marks.

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