Question 2
In a positive-edge-triggered D flipflop, if the D input is 0 and the clock signal transitions from low to high, Q output is 1.
TRUE
FALSE
Question 2: In a positive-edge-triggered D flipflop, if the D input i…
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FALSE
Question 2 of 15 in the IIT Madras BS Computer System Design (Computer System Design) Quiz 2 paper sat on 3 Dec 2023, in the September 2023 term (IIT M DEGREE AN2 EXAM QDB2 03 Dec 2023). It carries 1 mark.
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