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Computer System Design, Quiz 2

September 2023 term, 3 Dec 2023, Set QDB2

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Question 1

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In a J-K flipflop, when J = 0 and K = 0, it toggles the flipflop’s state.

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A.
TRUE
B.
FALSE

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In a J-K flipflop, when J = 0 and K = 0, it toggles the flipflop’s state. In a positive-edge-triggered D flipflop, if the D input is 0 and the clock signal transitions from low to high, Q output is 1. In a NAND-based gated D latch, when the *write enable* input is 0, it denotes the Memory Hold state.