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September 2025 term · Computer System Design · BSCS3031

Computer System Design End Term: 21 December 2025 (September 2025 term)

The IIT Madras BS Computer System Design (Computer System Design) End Term paper sat on 21 Dec 2025, in the September 2025 term: 20 questions for 50 marks in 180 minutes. Every question is below with its answer. Take it as a timed mock test to be marked, or read it through first.

Questions
20
Marks
50
Duration
180 min
MCQ
8
Numerical
10
Written
2
Take as mock testPractise with answers

Updated

Official paper: Computer System Design 18 Dec 25 · No negative marking.

Question 1

+1 markOne correct option

A multiplexer is a combinational circuit that selects one input from multiple inputs and forwards it to a single output.

  1. A

    True

  2. B

    False

Show answer

Correct answer

  • A

    True

Question 1 on its own page

Question 2

+1 markOne correct option

A JK flip-flop cannot store information without a continuous clock input.

  1. A

    True

  2. B

    False

Show answer

Correct answer

  • B

    False

Question 2 on its own page

Question 3

+1 markOne correct option

In a 4-bit system, the two's complement of a binary number 1010 can be represented as -6.

  1. A

    True

  2. B

    False

Show answer

Correct answer

  • A

    True

Question 3 on its own page

Question 4

+1 markOne correct option

A decoder performs the inverse operation of a multiplexer.

  1. A

    True

  2. B

    False

Show answer

Correct answer

  • A

    True

Question 4 on its own page

Question 5

+1 markOne correct option

According to Moore's Law, the size of transistors on an integrated circuit doubles approximately every two years.

  1. A

    True

  2. B

    False

Show answer

Correct answer

  • B

    False

Question 5 on its own page

Question 6

+3 marksNumerical answer
Show answer

Correct answer: 8

Question 6 on its own page

Question 7

+3 marksOne correct option
  1. A

    OR, NOR

  2. B

    OR, NAND

  3. C

    AND, NAND

  4. D

    AND, NOR

  5. E

    None of these

Show answer

Correct answer

  • B

    OR, NAND

Question 7 on its own page

Question 8

+3 marksNumerical answer
Show answer

Correct answer: 1

Question 8 on its own page

Question 9

+3 marksNumerical answer

Given that NOT, 2-input AND/OR gates have delays of 1 ns, what will be the maximum delay of a 2x1 multiplexer circuit? Note: if the answer is 1 ns, write 1.

Show answer

Correct answer: 3

Question 9 on its own page

Question 10

+3 marksNumerical answer

Consider the circuit consisting of three D flipflops and one NAND gate as shown below. The initial states are Q1=1, Q2=0, and Q3=1. What is the output after (Q1,Q2,Q3) after 4 clock pulse?

Note: If answer if Q1=0, Q2=0,Q3=0, then write 000

Show answer

Correct answer: 111

Question 10 on its own page

Question 11

+3 marksNumerical answer

A processor uses the following control word format:

How many registers can be addressed in the register bank?

Show answer

Correct answer: 32

Question 11 on its own page

Question 12

+3 marksNumerical answer
Show answer

Correct answer: 10111010

Question 12 on its own page

Question 13

+3 marksOne correct option

Choose the correct truth table according to the given Boolean expression:

  1. A

    (A figure from the original paper is missing from the source site.)

  2. B
  3. C

    (A figure from the original paper is missing from the source site.)

  4. D

    (A figure from the original paper is missing from the source site.)

Show answer

Correct answer

  • C

    (A figure from the original paper is missing from the source site.)

Question 13 on its own page

Question 14

+3 marksWritten answer

Consider a common bus architecture containing memory and three registers: A, B, and C. The control word format is shown below.

What would be the control word if you intend to perform a register transfer from register A to register B? Note: Provide your answer in hexadecimal format (e.g., 0x3A). Answers Case Sensitive : No

Show answer

Correct answer: 0x18

Question 14 on its own page

Question 15

+3 marksNumerical answer
Show answer

Correct answer: 22

Question 15 on its own page

Question 16

+3 marksWritten answer

Answers Case Sensitive : No

Show answer

Correct answer: 0x2F46

Question 16 on its own page

Question 17

+3 marksNumerical answer

Consider a gated D-Latch constructed using NAND gates. The initial input (at 0 ns) is D = 1, and the write enable is high. The write enable toggles between high and low every 5 ns. The input D changes from 0 to 1 and from 1 to 0 every 6 seconds. What will be the output Q after 16 ns?

Show answer

Correct answer: 1

Question 17 on its own pageAlso asked in Quiz 2 24 Mar 2024

Question 18

+3 marksOne correct option

In the circuit shown below, D1 and D2 are positive edge triggered D flipflops, x1 and x2 are inputs of D1 and D2 flipflop. Choose the correct timing diagram of the output Y.

  1. A

    (A figure from the original paper is missing from the source site.)

  2. B

    (A figure from the original paper is missing from the source site.)

  3. C

    (A figure from the original paper is missing from the source site.)

  4. D

    (A figure from the original paper is missing from the source site.)

  5. E

    None of these

Show answer

Correct answer

  • C

    (A figure from the original paper is missing from the source site.)

Question 18 on its own page

Question 19

+3 marksNumerical answer

Consider the circuit diagram as shown below. Assuming it was initially cleared to 0, state the output(Y) for the next 4 clock pulses.

Show answer

Correct answer: 1111

Question 19 on its own page

Question 20

+3 marksNumerical answer
Show answer

Correct answer: 4

Question 20 on its own page