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May 2025 term · Computer System Design · BSCS3031

Computer System Design End Term: 31 August 2025, Set QDB1 (May 2025 term)

The IIT Madras BS Computer System Design (Computer System Design) End Term paper sat on 31 Aug 2025, in the May 2025 term, set QDB1: 20 questions for 50 marks in 180 minutes. Every question is below with its answer. Take it as a timed mock test to be marked, or read it through first.

Questions
20
Marks
50
Duration
180 min
MCQ
6
Numerical
12
Written
2

Updated

Official paper: IIT M DEGREE AN EXAM QDB3 31 Aug 2025 · No negative marking.

Question 1

+1 markOne correct option

In a 4-bit system, the one’s complement of the binary number 1100 is 0011.

  1. A

    True

  2. B

    False

Show answer

Correct answer

  • A

    True

Question 2

+1 markOne correct option

A synchronous counter triggers all flipflops using a common clock signal, while an asynchronous counter triggers each flipflop using the output of the previous flipflop.

  1. A

    True

  2. B

    False

Show answer

Correct answer

  • A

    True

Question 3

+1 markOne correct option

In a system with 64 unique states, 6 flipflops are sufficient to represent all the states.

  1. A

    True

  2. B

    False

Show answer

Correct answer

  • A

    True

Question 4

+1 markOne correct option

In a decoder, at any point, exactly one of the outputs is 1 and all the rest are 0s.

  1. A

    True

  2. B

    False

Show answer

Correct answer

  • A

    True

Question 5

+1 markOne correct option

According to Moore’s law, if a computer system has 2 million transistors today, then it will have approximately 32 million transistors in 8 years.

  1. A

    True

  2. B

    False

Show answer

Correct answer

  • A

    True

Question 6

+3 marksOne correct option
  1. A
  2. B
  3. C
  4. D
  5. E
Show answer

Correct answer

  • E

Question 7

+3 marksNumerical answer
Show answer

Correct answer: 3

Question 8

+3 marksNumerical answer
Show answer

Correct answer: 5

Question 9

+3 marksNumerical answer
Show answer

Correct answer: 5

Question 10

+3 marksNumerical answer
Show answer

Correct answer: 2

Question 11

+3 marksNumerical answer
Show answer

Correct answer: 6

Question 12

+3 marksNumerical answer
Show answer

Correct answer: 3

Question 13

+3 marksNumerical answer

Consider a mod-12 up counter with an initial state of 0011. What will be the state of the counter after 25 clock pulses?

Show answer

Correct answer: 0100

Question 14

+3 marksNumerical answer
Show answer

Correct answer: 0000

Question 15

+3 marksNumerical answer

Consider a 9-bit Johnson counter. What is the total number of unique states it can cycle through?

Show answer

Correct answer: 18

Question 16

+3 marksWritten answer

Consider a common bus architecture comprising of memory, and registers X, Y, Z.

The control word format is given below.

MemoryRegister XRegister YRegister Z
ReadWriteInputOutputInputOutputInputOutput

What would be the control word if you intend to perform a register transfer from register Y to register Z?

Note: Enter the value in hexadecimal format(e.g. 0x24).

Show answer

Correct answer: 0x06

Question 17

+3 marksNumerical answer
Show answer

Correct answer: 24

Question 18

+3 marksNumerical answer
Show answer

Correct answer: 4

Question 19

+3 marksWritten answer

Suppose we want to execute a data movement instruction, where we move the data present in register R3R_3 to register R21R_{21}.

Instruction: MOV Rd,RrR_d, R_r

RdR_d: Destination register, RrR_r: Source register

Operands: 0≤d≤31,0≤r≤310 \le d \le 31, 0 \le r \le 31

Instruction Format:

001011rddrdrrrdd

What will be the hexadecimal machine code for the instruction?

Note: Enter the value in hexadecimal format (e.g., 0x2438).

Show answer

Correct answer: 0x2D4D

Question 20

+3 marksNumerical answer
Show answer

Correct answer: 11101010