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Computer System Design · Quiz 2 · 24 Mar 2024 · January 2024 term

Question 4: In a positive-edge-triggered D flipflop, if the D input i…

Question 4

+1 markOne correct option

In a positive-edge-triggered D flipflop, if the D input is 1 and the clock signal transitions from low to high, Q output is 0.

  1. A

    TRUE

  2. B

    FALSE

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Correct answer

  • B

    FALSE

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Question 4 of 15 in the IIT Madras BS Computer System Design (Computer System Design) Quiz 2 paper sat on 24 Mar 2024, in the January 2024 term (IIT M DEGREE AN EXAM QDB2 24 Mar 2024). It carries 1 mark.

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