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Computer System Design · Quiz 2 · 24 Mar 2024 · January 2024 term

Question 14: Consider a gated D-Latch constructed using NAND gates. T…

Question 14

+4 marksNumerical answer

Consider a gated D-Latch constructed using NAND gates. The initial input (at 0 ns) is D = 1, and the write enable is high. The write enable toggles between high and low every 5 ns. The input D changes from 0 to 1 and from 1 to 0 every 6 seconds. What will be the output Q after 16 ns?

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Question 14 of 15 in the IIT Madras BS Computer System Design (Computer System Design) Quiz 2 paper sat on 24 Mar 2024, in the January 2024 term (IIT M DEGREE AN EXAM QDB2 24 Mar 2024). It carries 4 marks.

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