Question 1
In a J-K flipflop, when J = 0 and K = 0, it toggles the flipflop’s state.
TRUE
FALSE
Question 2
In a positive-edge-triggered D flipflop, if the D input is 0 and the clock signal transitions from low to high, Q output is 1.
TRUE
FALSE
Question 3
In a NAND-based gated D latch, when the write enable input is 0, it denotes the Memory Hold state.
TRUE
FALSE
12 more questions in this paper
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More on the Computer System Design Quiz 2 3 Dec 2023 paper
The IIT Madras BS Computer System Design (Computer System Design) Quiz 2 paper sat on 3 Dec 2023, in the September 2023 term: 15 questions for 50 marks in 120 minutes. The first 3 questions are below. Sign in with Google — it is free — to see the whole paper with its answers and explanations, in learning mode or as a timed mock test.
| Feature | Computer System Design Quiz 2 3 Dec 2023 at a glance |
|---|---|
| Term | September 2023 term |
| Subject | Computer System Design |
| Course code | BSCS3031 |
| Questions | 15 |
| Marks | 50 |
| Duration | 120 min |
| MCQ | 11 |
| Numerical | 2 |
| MSQ | 2 |
| Official paper | IIT M DEGREE AN2 EXAM QDB2 03 Dec 2023 |
| Negative marking | No negative marking. |
| Updated |