Question 1
Consider the circuit diagram shown below:
Given that we only have 2:1 mux gates, what is the minimum number of mux gates needed to represent the circuit diagram above?
Computer System Design Quiz 1: 19 July 2026 (May 2026 term)
The IIT Madras BS Computer System Design (Computer System Design) Quiz 1 paper sat on 19 Jul 2026, in the May 2026 term: 12 questions for 50 marks in 120 minutes. Every question is below with its answer. Take it as a timed mock test to be marked, or read it through first.
- 12
- 50
- 120 min
- 6
- 6
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Correct answer: 3
Question 2
Answer the following question based on given timing diagram.
Given that we only have 2-input XOR gates, what is the minimum number of XOR gates needed to represent a circuit with an output timing diagram same as Y?
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Correct answer: 2
Question 3
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Correct answer: 1
Question 4
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Correct answer: 4
Question 5
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Correct answer: 10
Question 6
A 4×16 decoder is implemented using NOT gates (delay = 1 ns) and 4-input AND gates (delay = 2 ns). What is the maximum delay from any input to any output?
Note: If the answer is 4 ns, write 4.
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Correct answer: 3
Question 7
None of these
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Correct answer
Question 8
0.75
0.33
0.25
1
0.50
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Correct answer
0.50
Question 9
None of these
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Correct answer
Question 10
2 or more inputs are at logic 0
2 or more inputs are at logic 1
Any odd number of inputs are at logic 0
Any odd number of inputs are at logic 1
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Correct answer
Any odd number of inputs are at logic 0
Question 11
What will be the output of the given circuit, as shown below?
1
0
X
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Correct answer
Question 12
a = 3, b = 4
a = 4, b = 5
a = 5, b = 6
a = 6, b = 7
a = 7, b = 8
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Correct answer
a = 5, b = 6