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Computer System Design · Quiz 1 · 19 Jul 2026 · May 2026 term

Question 6: A 4×16 decoder is implemented using NOT gates (delay = 1 …

Question 6

+3 marksNumerical answer

A 4×16 decoder is implemented using NOT gates (delay = 1 ns) and 4-input AND gates (delay = 2 ns). What is the maximum delay from any input to any output?
Note: If the answer is 4 ns, write 4.

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Correct answer: 3

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Question 6 of 12 in the IIT Madras BS Computer System Design (Computer System Design) Quiz 1 paper sat on 19 Jul 2026, in the May 2026 term (Computer Systems Design 16 Jul 26). It carries 3 marks.

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