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January 2024 term · Computer System Design · BSCS3031

Computer System Design End Term: 28 April 2024, Set QDB3 (January 2024 term)

The IIT Madras BS Computer System Design (Computer System Design) End Term paper sat on 28 Apr 2024, in the January 2024 term, set QDB3: 20 questions for 50 marks in 180 minutes. Every question is below with its answer. Take it as a timed mock test to be marked, or read it through first.

Questions
20
Marks
50
Duration
180 min
MCQ
8
Numerical
10
Written
2

Updated

Official paper: IIT M DEGREE AN EXAM QDB3 28 Apr 2024 · No negative marking.

Question 1

+1 markOne correct option

In a 4-bit system, the one’s complement of the binary number 0001 is 1110.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • A

    TRUE

Question 2

+1 markOne correct option

An asynchronous counter uses a common clock signal to trigger all flipflops, while a synchronous counter uses the output of each flipflop to trigger the next flipflop.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 3

+1 markOne correct option

In a system with 65 unique states, 5 flipflops are sufficient to represent all the states.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 4

+1 markOne correct option

In a decoder, at any point, exactly one of the outputs is 0 and all the rest are 1s.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 5

+1 markOne correct option

According to Moore’s law, if a computer system has 2 million transistors today, then it will have approximately 64 million transistors in 8 years.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 6

+3 marksOne correct option
  1. A
  2. B
  3. C
  4. D
Show answer

Correct answer

  • A

Question 7

+3 marksOne correct option
  1. A

    Two input XNOR gate as with Y and Z as input

  2. B

    Two input XNOR gate as with X and Y as input

  3. C

    Two input XOR gate as with X and Y as input

  4. D

    Two input NOR gate as with Y and Z as input

  5. E

    Two input NAND gate as with X and Y as input

Show answer

Correct answer

  • C

    Two input XOR gate as with X and Y as input

Question 8

+3 marksOne correct option
  1. A
  2. B
  3. C
  4. D
  5. E
Show answer

Correct answer

  • D

Question 9

+3 marksNumerical answer
Show answer

Correct answer: 2

Question 10

+3 marksNumerical answer
Show answer

Correct answer: 5

Question 11

+3 marksNumerical answer

A circuit has four inputs (A, B, C and D) and a single output Y. Y is set to logic one if A is equal to B and C is equal to D, otherwise, Y is set to logic zero. How many maxterms present in the POS expression for Y?

Show answer

Correct answer: 12

Question 12

+3 marksNumerical answer
Show answer

Correct answer: 3

Question 13

+3 marksNumerical answer

What is the minimum number of flipflops required to construct a 5-bit Johnson counter, assuming that all the basic gates are available?

Show answer

Correct answer: 4

Question 14

+3 marksNumerical answer
Show answer

Correct answer: 1100

Question 15

+3 marksNumerical answer

If we implement a simple memory array with 8-bit addressability and address space size of 20 bits, then what would be the total size of the memory (in bits)?

Show answer

Correct answer: 160

Question 16

+3 marksWritten answer

Consider a common bus architecture comprising of memory, and registers X, Y, Z.
The control word format is given below.

MemoryRegister XRegister YRegister Z
ReadWriteInputOutputInputOutputInputOutput

What would be the control word if you intend to perform a register transfer from register Y to register X?
Note: Enter the value in hexadecimal format(e.g. 0x12).

Show answer

Correct answer: 0x24

Question 17

+3 marksNumerical answer

Let a processor contain 32 registers in its register file. Consider that the ALU is capable of performing 4 different operations: addition, subtraction, AND, and XNOR. What is the minimum number of bits required by an instruction in order to perform addition between two operands stored in the register file and then store the result in the register containing the first operand?

Show answer

Correct answer: 12

Question 18

+3 marksNumerical answer
Show answer

Correct answer: 32

Question 19

+3 marksWritten answer

Suppose we want to execute a data movement instruction, where we move the data present in register R30R_{30} to register R23R_{23}.
Instruction: MOV RdR_d, RrR_r
RdR_d: Destination register, RrR_r: Source register
Operands: 0≤d≤31,0≤r≤310 \le d \le 31, 0 \le r \le 31
Instruction Format:

001011drdrdrrdrd

What will be the hexadecimal machine code for the instruction?

Show answer

Correct answer: 0x2FBE

Question 20

+3 marksNumerical answer
Show answer

Correct answer: 11111000