Question 1
The primary purpose of Hardware Description Languages (HDLs) is to model software behavior within hardware.
TRUE
FALSE
Question 2
A positive-edge-triggered D flip-flop updates its output (Q) based on the D input only when the clock signal transitions from high to low.
TRUE
FALSE
Question 3
The initial block in verilog will executes once at time t=0, and $finish stops the simulation completely.
TRUE
FALSE
24 more questions in this paper
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More on the Digital System Design End Term 13 Apr 2025 Set QEF1 paper
The IIT Madras BS Digital System Design (Digital System Design) End Term paper sat on 13 Apr 2025, in the January 2025 term, set QEF1: 27 questions for 50 marks in 180 minutes. The first 3 questions are below. Sign in with Google — it is free — to see the whole paper with its answers and explanations, in learning mode or as a timed mock test.
| Feature | Digital System Design End Term 13 Apr 2025 Set QEF1 at a glance |
|---|---|
| Term | January 2025 term |
| Subject | Digital System Design |
| Course code | EE2103 |
| Questions | 27 |
| Marks | 50 |
| Duration | 180 min |
| MCQ | 26 |
| MSQ | 1 |
| Official paper | IIT M ES FOUNDATION AN EXAM QEF3 13 Apr 2025 |
| Negative marking | No negative marking. |
| Updated |
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