Question 1
For the given Voltage Transfer Characteristic(VTC) of an Inverter, the minimum input voltage to treat as logic High is 2 V.
TRUE
FALSE
Question 2
TRUE
FALSE
Question 3
The largest n-bit signed number in 2’s complement representation consists of n ones.
TRUE
FALSE
25 more questions in this paper
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More on the Digital Systems End Term 13 Apr 2025 Set QEF3 paper
The IIT Madras BS Digital Systems (Digital Systems) End Term paper sat on 13 Apr 2025, in the January 2025 term, set QEF3: 28 questions for 50 marks in 180 minutes. The first 3 questions are below. Sign in with Google — it is free — to see the whole paper with its answers and explanations, in learning mode or as a timed mock test.
| Feature | Digital Systems End Term 13 Apr 2025 Set QEF3 at a glance |
|---|---|
| Term | January 2025 term |
| Subject | Digital Systems |
| Course code | EE1102 |
| Questions | 28 |
| Marks | 50 |
| Duration | 180 min |
| MCQ | 23 |
| Numerical | 2 |
| MSQ | 3 |
| Official paper | IIT M ES FOUNDATION AN EXAM QEF3 13 Apr 2025 |
| Negative marking | No negative marking. |
| Updated |
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