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Computer System Design · Quiz 2 · 3 Aug 2025 · May 2025 term

Question 4: In a positive-edge-triggered D flipflop, if the D input i…

Question 4

+1 markOne correct option

In a positive-edge-triggered D flipflop, if the D input is 1 and the clock signal transitions from low to high, Q output is 0.

  1. A

    TRUE

  2. B

    FALSE

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Correct answer

  • B

    FALSE

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Question 4 of 15 in the IIT Madras BS Computer System Design (Computer System Design) Quiz 2 paper sat on 3 Aug 2025, in the May 2025 term (IIT M IMPROVEMENT AN EXAM QIM2 03 Aug 2025). It carries 1 mark.

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