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Computer System Design · End Term · 24 Dec 2023 · September 2023 term · Set ADB3

Question 2: In a positive-edge-triggered D flipflop, if the D input i…

Question 2

+1 markOne correct option

In a positive-edge-triggered D flipflop, if the D input is 1 and the clock signal transitions from low to high, Q output is 0.

  1. A

    TRUE

  2. B

    FALSE

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Correct answer

  • B

    FALSE

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Question 2 of 20 in the IIT Madras BS Computer System Design (Computer System Design) End Term paper sat on 24 Dec 2023, in the September 2023 term (IIT M IMPROVEMENT FN EXAM FDI2 24 Dec 2023). It carries 1 mark.

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