Opening the paper…

FPGA Design, Quiz 1

September 2025 term, 26 Oct 2025, Set QEB2

Learning mode

Question 1

+2−0Single correct

Select one option

A.
The data is first stored in main memory and later transferred to the peripheralby DMA.
B.
The write operation directly updates the peripheral’s hardware registermapped at that address.
C.
The CPU triggers an interrupt to notify the peripheral of new data.
D.
The value is cached and updated only after multiple writes.

Report a problem

to report a problem with this question.

Choose a question

Answered: 0
Not answered: 1
Marked for review: 0
Answered & marked for review: 0
Not visited: 12

Discussion

Submit this paper?

You cannot change your answers after submitting.

Answered: 0
Not answered: 1
Marked for review: 0
Answered & marked for review: 0
Not visited: 12

Instructions

The palette shows the status of every question. Pick a number to go straight to it.

Answered: 0
Not answered: 1
Marked for review: 0
Answered & marked for review: 0
Not visited: 12

Save & Next moves to the next question. Answers are saved as you go.
Mark for Review & Next flags the question to come back to. A flagged answer still counts.
Clear Response removes your answer to the question on screen.
The ← and → keys move to the previous and next question.

Figure from the original question paper Which of the following best explains the difference between **user space** and **kernel space**? Figure from the original question paper