Question 1

1 1  #define UART_BASE 0xB0005000
2 2  void init_uart(){
3 3      u16 *baud_reg = (u16*)UART_BASE;
4 4      *baud_reg = 0x7D;
5 5  }
6 6  u32 read_uart(){
7 7      u32 *rx_reg = (u32*)(UART_BASE + 8);
8 8      u8 *status_reg = (u8*)(UART_BASE + 12);
9 9      while((*status_reg & 0x4) == 0);
1010      return *rx_reg;
1111  }

Consider the code segment (for xv6) given below. 1 #define UART_BASE 0xB0005000 2 void init_uart(){ 3 u16 *baud_reg = (u16*)UART_BASE; 4 *baud_reg = 0x7D; 5 } 6 u32 read_uart(){ 7 u32 *rx_reg = (u32*)(UART_BASE + 8); 8 u8 *status_reg = (u8*)(UART_BASE + 12); 9 while((*status_reg & 0x4) == 0); 10 return *rx_reg; 11 } What are the base address and the end address of the *RX register*? If the memory map of the DMA controller starts from the offset 0x30001000 and has an address range of 256 bytes in a 32-bit addressing scheme, what will be the final address in the memory map? Consider the following program snippet: 1 void exampleFunction(int x, int y) 2 { 3 char smallBuffer[4]; 4 char largeBuffer[8]; 5 } 6 void main 7 { 8 exampleFunction(1, 2); 9 } When `largeBuffer[8] = smallBuffer[0]` occurs, the situation is known as \_\_\_.