System Design with Verilog and VLSI Quiz 1: 26 October 2025, Set QEB2 (September 2025 term)

The IIT Madras BS System Design with Verilog and VLSI (System Design with Verilog and VLSI) Quiz 1 paper sat on 26 Oct 2025, in the September 2025 term, set QEB2: 1 question for 20 marks in 120 minutes. Every question is below with its answer. Take it as a timed mock test to be marked, or read it through first.