Figure from the original question paper

(B) The write operation directly updates the peripheral’s hardware registermapped at that address.

(A) The data is first stored in main memory and later transferred to the peripheralby DMA.

(C) The CPU triggers an interrupt to notify the peripheral of new data.

(D) The value is cached and updated only after multiple writes.

FPGA Design · Quiz 1 · 26 Oct 2025 · September 2025 term · Set QEB2

Embedded Linux and FPGAs Quiz 1 26 Oct 2025 — Question 1

Question 1

+2 marksOne correct option

A
The data is first stored in main memory and later transferred to the peripheralby DMA.
B
The write operation directly updates the peripheral’s hardware registermapped at that address.
C
The CPU triggers an interrupt to notify the peripheral of new data.
D
The value is cached and updated only after multiple writes.

Show answer

Correct answer

B
The write operation directly updates the peripheral’s hardware registermapped at that address.

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Question 1 of 13 in the IIT Madras BS FPGA Design (Embedded Linux and FPGAs) Quiz 1 paper sat on 26 Oct 2025, in the September 2025 term (IIT M ES DEGREE AN EXAM QEB4 26 Oct). It carries 2 marks.

Embedded Linux and FPGAs Quiz 1 26 Oct 2025 — Question 1

Question 1

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