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January 2025 term · Digital System Design · EE2103

Digital System Design Quiz 2: 16 March 2025 (January 2025 term)

The IIT Madras BS Digital System Design (Digital System Design) Quiz 2 paper sat on 16 Mar 2025, in the January 2025 term: 25 questions for 40 marks in 120 minutes. Every question is below with its answer. Take it as a timed mock test to be marked, or read it through first.

Questions
25
Marks
40
Duration
120 min
MCQ
23
MSQ
2
Take as mock testPractise with answers

Updated

Official paper: IIT M ES FOUNDATION AN EXAM QEF2 16 Mar 2025 · No negative marking.

Question 1

+1 markOne correct option

Modularity increases complexity by breaking the design into smaller components, making maintenance and verification more difficult.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 1 on its own page

Question 2

+1 markOne correct option

To efficiently divide an unsigned number N by 8 using bitwise operations, shift N right by log2(8) positions.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • A

    TRUE

Question 2 on its own page

Question 3

+1 markOne correct option

A parallel multiplier with a ripple-carry structure reduces latency.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 3 on its own page

Question 4

+1 markOne correct option

If the immediate assertion in SystemVerilog fails, the simulation will continue while displaying an error message.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • A

    TRUE

Question 4 on its own page

Question 5

+1 markOne correct option

A 64-byte memory implemented using 6T SRAM requires 384 transistors.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 5 on its own page

Question 6

+1 markOne correct option

In a FIFO design, when the read and write pointers are equal, the "Full" status flag is asserted.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 6 on its own page

Question 7

+1 markOne correct option

In a register bank, increasing fan-out decreases the output delay of a register.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • B

    FALSE

Question 7 on its own page

Question 8

+1 markOne correct option

When the CPU is reset, the program counter (PC) goes to a defined start point.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • A

    TRUE

Question 8 on its own page

Question 9

+1 markOne correct option

If the branch condition is false, the PC advances normally to execute the next instruction in sequence.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • A

    TRUE

Question 9 on its own page

Question 10

+1 markOne correct option

In a CPU with 5-bit immediate values using two's complement representation, the immediate value 5'b11001 corresponds to -7 in decimal.

  1. A

    TRUE

  2. B

    FALSE

Show answer

Correct answer

  • A

    TRUE

Question 10 on its own page

Question 11

+2 marksOne correct option

In a synchronous system operating at 200MHz, if a sequential multiplier requires 8 clock cycles to complete one multiplication, what is its throughput in operations per second?

  1. A

    20 thousand operations per second

  2. B

    40 thousand operations per second

  3. C

    8 million operations per second

  4. D

    25 million operations per second

Show answer

Correct answer

  • D

    25 million operations per second

Question 11 on its own page

Question 12

+2 marksOne correct option

If a memory module is configured as 4 x 16, how many bits does each memory location store?

  1. A

    4

  2. B

    8

  3. C

    16

  4. D

    64

Show answer

Correct answer

  • C

    16

Question 12 on its own page

Question 13

+2 marksOne correct option

How many bits are required to select one of the given basic operations (ADD, SUB, MUL, DIV) in a simple ALU?

  1. A

    1 bit

  2. B

    2 bits

  3. C

    3 bits

  4. D

    4 bits

Show answer

Correct answer

  • B

    2 bits

Question 13 on its own page

Question 14

+2 marksOne correct option

Consider the instruction format of the system is {destination_address,source_address1, OP, source_address2}.

text
The Operation(OP) Encoding are as follows:
    000 → ADD
    001 → SUB
    010 → MUL
    011 → DIV
    100 → AND
    101 → OR
    110 → NOT
Register Encoding as follows:
    000 → R0
    001 → R1
    010 → R2
    011 → R3
    100 → R4
    101 → R5
    110 → R6
    111 → R7

With the given data, What is the binary encoding of the instruction R3 = R1 * R2?

  1. A
  2. B
  3. C
  4. D
Show answer

Correct answer

  • D
Question 14 on its own page

Question 15

+2 marksOne correct option

Why is register r0 often hardwired to 0 in many architectures?

  1. A

    To simplify certain operations like initialization

  2. B

    To increase the number of available registers

  3. C

    To allow self-modifying code

  4. D

    To optimize cache memory

Show answer

Correct answer

  • A

    To simplify certain operations like initialization

Question 15 on its own page

Question 16

+2 marksOne or more correct options

Consider the given verilog code snippet, answer the given subquestions.

verilog
module sequential_multiplier (
input logic clk,                // Clock signal
input logic reset,              // Synchronous reset
input logic start,              // Start signal to begin multiplication
input logic [7:0] multiplicand, // Multiplicand input
input logic [7:0] multiplier,   // Multiplier input
output logic [15:0] product,    // Product output
output logic done               // Indicates completion
);


typedef enum logic [1:0] {IDLE, MULTIPLY, DONE} state_t;
state_t state;


logic [7:0] multiplicand_reg, multiplier_reg;
logic [15:0] product_reg;
int count;


always_ff @(posedge clk) begin
    if (reset) begin
        state <= IDLE;
        product_reg <= 16'b0;
        multiplicand_reg <= 8'b0;
        multiplier_reg <= 8'b0;
        count <= 0;
        done <= 0;
    end
    else begin
        case (state)
            IDLE: begin
                done <= 0;
                if (start) begin
                    multiplicand_reg <= multiplicand;
                    multiplier_reg <= multiplier;
                    product_reg <= 16'b0;
                    count <= 8;
                    state <= MULTIPLY;
                end
            end
verilog
            MULTIPLY: begin
                if (multiplier_reg[0]) // Check LSB of multiplier
                    product_reg <= product_reg + {8'b0,multiplicand_reg};
                multiplicand_reg <= multiplicand_reg << 1; // Shift left for
next partial sum
                multiplier_reg <= multiplier_reg >> 1;     // Shift right to
process next bit
                count <= count - 1;


                if (count == 0)
                    state <= DONE;


            end


            DONE: begin
                done <= 1;
                product <= product_reg;
                if (!start) // Wait for start to go low before resetting
                    state <= IDLE;
            end
        endcase
    end
end
endmodule

What is the role of the IDLE state in the FSM?

Select all that apply.

  1. A

    It keeps the system on standby until the start signal is activated.

  2. B

    It resets the product register before starting multiplication.

  3. C

    It verifies if the reset signal is enabled before processing begins.

  4. D

    It executes the final multiplication operation.

Show answer

Correct answers

  • A

    It keeps the system on standby until the start signal is activated.

  • B

    It resets the product register before starting multiplication.

Question 16 on its own page

Question 17

+2 marksOne correct option

Consider the given verilog code snippet, answer the given subquestions.

verilog
module sequential_multiplier (
input logic clk,                // Clock signal
input logic reset,              // Synchronous reset
input logic start,              // Start signal to begin multiplication
input logic [7:0] multiplicand, // Multiplicand input
input logic [7:0] multiplier,   // Multiplier input
output logic [15:0] product,    // Product output
output logic done               // Indicates completion
);


typedef enum logic [1:0] {IDLE, MULTIPLY, DONE} state_t;
state_t state;


logic [7:0] multiplicand_reg, multiplier_reg;
logic [15:0] product_reg;
int count;


always_ff @(posedge clk) begin
    if (reset) begin
        state <= IDLE;
        product_reg <= 16'b0;
        multiplicand_reg <= 8'b0;
        multiplier_reg <= 8'b0;
        count <= 0;
        done <= 0;
    end
    else begin
        case (state)
            IDLE: begin
                done <= 0;
                if (start) begin
                    multiplicand_reg <= multiplicand;
                    multiplier_reg <= multiplier;
                    product_reg <= 16'b0;
                    count <= 8;
                    state <= MULTIPLY;
                end
            end
verilog
            MULTIPLY: begin
                if (multiplier_reg[0]) // Check LSB of multiplier
                    product_reg <= product_reg + {8'b0,multiplicand_reg};
                multiplicand_reg <= multiplicand_reg << 1; // Shift left for
next partial sum
                multiplier_reg <= multiplier_reg >> 1;     // Shift right to
process next bit
                count <= count - 1;


                if (count == 0)
                    state <= DONE;


            end


            DONE: begin
                done <= 1;
                product <= product_reg;
                if (!start) // Wait for start to go low before resetting
                    state <= IDLE;
            end
        endcase
    end
end
endmodule

What condition causes the FSM to transition from MULTIPLY to DONE?

  1. A

    When the multiplicand is fully shifted left.

  2. B

    When count reaches zero.

  3. C

    When multiplier_reg becomes zero.

  4. D

    When start is deasserted.

Show answer

Correct answer

  • B

    When count reaches zero.

Question 17 on its own page

Question 18

+2 marksOne correct option

Consider the given verilog code snippet, answer the given subquestions.

verilog
module sequential_multiplier (
input logic clk,                // Clock signal
input logic reset,              // Synchronous reset
input logic start,              // Start signal to begin multiplication
input logic [7:0] multiplicand, // Multiplicand input
input logic [7:0] multiplier,   // Multiplier input
output logic [15:0] product,    // Product output
output logic done               // Indicates completion
);


typedef enum logic [1:0] {IDLE, MULTIPLY, DONE} state_t;
state_t state;


logic [7:0] multiplicand_reg, multiplier_reg;
logic [15:0] product_reg;
int count;


always_ff @(posedge clk) begin
    if (reset) begin
        state <= IDLE;
        product_reg <= 16'b0;
        multiplicand_reg <= 8'b0;
        multiplier_reg <= 8'b0;
        count <= 0;
        done <= 0;
    end
    else begin
        case (state)
            IDLE: begin
                done <= 0;
                if (start) begin
                    multiplicand_reg <= multiplicand;
                    multiplier_reg <= multiplier;
                    product_reg <= 16'b0;
                    count <= 8;
                    state <= MULTIPLY;
                end
            end
verilog
            MULTIPLY: begin
                if (multiplier_reg[0]) // Check LSB of multiplier
                    product_reg <= product_reg + {8'b0,multiplicand_reg};
                multiplicand_reg <= multiplicand_reg << 1; // Shift left for
next partial sum
                multiplier_reg <= multiplier_reg >> 1;     // Shift right to
process next bit
                count <= count - 1;


                if (count == 0)
                    state <= DONE;


            end


            DONE: begin
                done <= 1;
                product <= product_reg;
                if (!start) // Wait for start to go low before resetting
                    state <= IDLE;
            end
        endcase
    end
end
endmodule

What happens when multiplier_reg[0] is 1 in the MULTIPLY state?

  1. A

    The multiplicand is shifted left.

  2. B

    The multiplicand is added to the product register.

  3. C

    The FSM transitions to the DONE state.

  4. D

    The multiplier is added to the product register.

Show answer

Correct answer

  • B

    The multiplicand is added to the product register.

Question 18 on its own page

Question 19

+2 marksOne correct option

Consider the given verilog code snippet, answer the given subquestions.

verilog
module sequential_multiplier (
input logic clk,                // Clock signal
input logic reset,              // Synchronous reset
input logic start,              // Start signal to begin multiplication
input logic [7:0] multiplicand, // Multiplicand input
input logic [7:0] multiplier,   // Multiplier input
output logic [15:0] product,    // Product output
output logic done               // Indicates completion
);


typedef enum logic [1:0] {IDLE, MULTIPLY, DONE} state_t;
state_t state;


logic [7:0] multiplicand_reg, multiplier_reg;
logic [15:0] product_reg;
int count;


always_ff @(posedge clk) begin
    if (reset) begin
        state <= IDLE;
        product_reg <= 16'b0;
        multiplicand_reg <= 8'b0;
        multiplier_reg <= 8'b0;
        count <= 0;
        done <= 0;
    end
    else begin
        case (state)
            IDLE: begin
                done <= 0;
                if (start) begin
                    multiplicand_reg <= multiplicand;
                    multiplier_reg <= multiplier;
                    product_reg <= 16'b0;
                    count <= 8;
                    state <= MULTIPLY;
                end
            end
verilog
            MULTIPLY: begin
                if (multiplier_reg[0]) // Check LSB of multiplier
                    product_reg <= product_reg + {8'b0,multiplicand_reg};
                multiplicand_reg <= multiplicand_reg << 1; // Shift left for
next partial sum
                multiplier_reg <= multiplier_reg >> 1;     // Shift right to
process next bit
                count <= count - 1;


                if (count == 0)
                    state <= DONE;


            end


            DONE: begin
                done <= 1;
                product <= product_reg;
                if (!start) // Wait for start to go low before resetting
                    state <= IDLE;
            end
        endcase
    end
end
endmodule

Why does the FSM wait for start to go LOW before transitioning from DONE to IDLE?

  1. A

    To ensure the multiplication result is available before resetting.

  2. B

    To prevent immediate retriggering of multiplication.

  3. C

    To reset the product register to zero.

  4. D

    To avoid errors in shifting operations.

Show answer

Correct answer

  • B

    To prevent immediate retriggering of multiplication.

Question 19 on its own page

Question 20

+2 marksOne or more correct options

Consider the given verilog code snippet, answer the given subquestions.

verilog
module sequential_multiplier (
input logic clk,                // Clock signal
input logic reset,              // Synchronous reset
input logic start,              // Start signal to begin multiplication
input logic [7:0] multiplicand, // Multiplicand input
input logic [7:0] multiplier,   // Multiplier input
output logic [15:0] product,    // Product output
output logic done               // Indicates completion
);


typedef enum logic [1:0] {IDLE, MULTIPLY, DONE} state_t;
state_t state;


logic [7:0] multiplicand_reg, multiplier_reg;
logic [15:0] product_reg;
int count;


always_ff @(posedge clk) begin
    if (reset) begin
        state <= IDLE;
        product_reg <= 16'b0;
        multiplicand_reg <= 8'b0;
        multiplier_reg <= 8'b0;
        count <= 0;
        done <= 0;
    end
    else begin
        case (state)
            IDLE: begin
                done <= 0;
                if (start) begin
                    multiplicand_reg <= multiplicand;
                    multiplier_reg <= multiplier;
                    product_reg <= 16'b0;
                    count <= 8;
                    state <= MULTIPLY;
                end
            end
verilog
            MULTIPLY: begin
                if (multiplier_reg[0]) // Check LSB of multiplier
                    product_reg <= product_reg + {8'b0,multiplicand_reg};
                multiplicand_reg <= multiplicand_reg << 1; // Shift left for
next partial sum
                multiplier_reg <= multiplier_reg >> 1;     // Shift right to
process next bit
                count <= count - 1;


                if (count == 0)
                    state <= DONE;


            end


            DONE: begin
                done <= 1;
                product <= product_reg;
                if (!start) // Wait for start to go low before resetting
                    state <= IDLE;
            end
        endcase
    end
end
endmodule

Which of the following multiplicand values produces an incorrect output based on the behavior of the given sequential multiplier when the multiplier is 2?

Select all that apply.

  1. A

    127

  2. B

    128

  3. C

    64

  4. D

    255

Show answer

Correct answers

  • B

    128

  • D

    255

Question 20 on its own page

Question 21

+2 marksOne correct option

Read the following assembly code and answer the given subquestions : (Assume the instruction format as inst dest, src1, src2 or inst dest, src1, immediate/offset)

asm
    ADDI r2, r0, 0
    ADDI r1, r0, 10
loop: BEQ  r1, r0, done
    LOAD r4, r3, 0
    SUBI r1, r1, 1
    ADD  r2, r2, r4
    ADDI r3, r3, 4
    ADDI r1, r0, 1
    JUMP loop
done: ADD r1,r1,r2

What is the purpose of this assembly program?

  1. A

    To find the maximum value in an array

  2. B

    To compute the sum of 10 elements in an array

  3. C

    Run an infinite loop due to incorrect loop control

  4. D

    To count the number of elements in an array

Show answer

Correct answer

  • C

    Run an infinite loop due to incorrect loop control

Question 21 on its own page

Question 22

+2 marksOne correct option

Read the following assembly code and answer the given subquestions : (Assume the instruction format as inst dest, src1, src2 or inst dest, src1, immediate/offset)

asm
    ADDI r2, r0, 0
    ADDI r1, r0, 10
loop: BEQ  r1, r0, done
    LOAD r4, r3, 0
    SUBI r1, r1, 1
    ADD  r2, r2, r4
    ADDI r3, r3, 4
    ADDI r1, r0, 1
    JUMP loop
done: ADD r1,r1,r2

What does the instruction BEQ r1, r0, done do?

  1. A

    Checks if r1 is zero and exits the loop if true

  2. B

    Compares r1 and r0, then jumps to done if they are different

  3. C

    Resets r1 to zero

  4. D

    Checks if r1 is zero and enter into the loop if true

Show answer

Correct answer

  • A

    Checks if r1 is zero and exits the loop if true

Question 22 on its own page

Question 23

+2 marksOne correct option

Read the following assembly code and answer the given subquestions : (Assume the instruction format as inst dest, src1, src2 or inst dest, src1, immediate/offset)

asm
    ADDI r2, r0, 0
    ADDI r1, r0, 10
loop: BEQ  r1, r0, done
    LOAD r4, r3, 0
    SUBI r1, r1, 1
    ADD  r2, r2, r4
    ADDI r3, r3, 4
    ADDI r1, r0, 1
    JUMP loop
done: ADD r1,r1,r2

What is the effect of ADDI r1, r0, 1 inside the loop?

  1. A

    Decreases r1 by 1

  2. B

    Resets r1 to 1 in every iteration

  3. C

    Increments r1 by 1 in each iteration

  4. D

    Moves the next memory address to r1

Show answer

Correct answer

  • B

    Resets r1 to 1 in every iteration

Question 23 on its own page

Question 24

+2 marksOne correct option

Read the following assembly code and answer the given subquestions : (Assume the instruction format as inst dest, src1, src2 or inst dest, src1, immediate/offset)

asm
    ADDI r2, r0, 0
    ADDI r1, r0, 10
loop: BEQ  r1, r0, done
    LOAD r4, r3, 0
    SUBI r1, r1, 1
    ADD  r2, r2, r4
    ADDI r3, r3, 4
    ADDI r1, r0, 1
    JUMP loop
done: ADD r1,r1,r2

What is stored in register r2 at the end of execution?

  1. A

    The sum of 10 elements of the array

  2. B

    The last element of the array

  3. C

    An unknown value

  4. D

    The memory address of the last accessed element

Show answer

Correct answer

  • C

    An unknown value

Question 24 on its own page

Question 25

+2 marksOne correct option

Read the following assembly code and answer the given subquestions : (Assume the instruction format as inst dest, src1, src2 or inst dest, src1, immediate/offset)

asm
    ADDI r2, r0, 0
    ADDI r1, r0, 10
loop: BEQ  r1, r0, done
    LOAD r4, r3, 0
    SUBI r1, r1, 1
    ADD  r2, r2, r4
    ADDI r3, r3, 4
    ADDI r1, r0, 1
    JUMP loop
done: ADD r1,r1,r2

What would happen if JUMP loop were removed?

  1. A

    The loop would run as expected

  2. B

    The program would execute only once

  3. C

    The sum would always be zero

  4. D

    The program would exit after the first iteration

Show answer

Correct answer

  • D

    The program would exit after the first iteration

Question 25 on its own page