Question 10
None of these
Computer System Design Quiz 2 16 Aug 2026 — Question 10
Show answer
Correct answer
Question 10 of 15 in the IIT Madras BS Computer System Design (Computer System Design) Quiz 2 paper sat on 16 Aug 2026, in the May 2026 term (Computer Systems Design 16 Aug 26). It carries 4 marks.
More questions from this paper
- In a J-K flipflop, when J = 1 and K = 1, it toggles the flipflop’s state.
- A multiplexer is a digital circuit that selects one of the several input signals and forwards it to a single output lin…
- In a NAND-based gated D latch, when the write enable input is 0, it denotes the Memory Hold state.
- In a positive-edge-triggered D flipflop, if the D input is 1 and the clock signal transitions from low to high, Q outpu…
- Sequential circuits do not utilize feedback loops, while combinational circuits do.
- Figure question
- Consider a gated D-Latch constructed using NAND gates. The initial input (at t=0 ns) is D=1, and the write enable (WE) …
- Consider the J-K flipflop circuit shown below. Assuming the flipflop is initially set to 1, what will be the output seq…
- Consider the circuit consisting of three D flipflops and one NAND gate as shown below. The initial states are Q1=0, Q2=…
- Figure question
- Figure question
- Choose the correct option:
- For the circuit shown in Figure 1, D1 and D2 are positive-edge-triggered D flip-flops with inputs x1 and x2 respectivel…
- We want to implement a circuit that outputs the sequence changing from 00 → 11 → 10 → 01 → 00 using J-K flipflops, as s…